1. Field of the Invention
The present invention relates to non-volatile memory, and in particular relates to a data managing method for the non-volatile memory.
2. Description of the Related Art
Flash memory is a kind of non-volatile memory which has developed rapidly in recent years. With low power consumption, small size and reliability, flash memory has become a popular auxiliary memory in computers. FIG. 1 is a schematic diagram of the flash memory. The flash memory apparatus 100 comprising a controller 102 and a flash chip 104 is used to transmit data with a host 110. The controller 102 uses a control line 106 to enable the flash chip 104 so that the flash chip 104 could be accessed by the controller 102. Moreover, those skilled in the art know that there is a translation table in the controller 102 having a function to translate logical block address (LBA) into physical block address (PBA). Therefore, data D0˜D4 respectively corresponding to LBA L00˜L04 (not shown in FIG. 1) are respectively stored into the PBA A00˜A04 in the block A of the flash chip 104.
Additionally, the flash chip 104 has several features that are (1) using a page, which is equal to 2K bytes, as a minimum unit to be read or written; while (2) using a block, which equals to about 64 pages (about 128K bytes), as a minimum unit to be erased. Based on those limitations, one should consider that in many respects operating flash memory, and managing flash memory is quite important.
FIG. 2 is an illustrative diagram showing the updating process performed in the flash memory. Referring to FIGS. 1 and 2, when performing the updating process, the flash memory apparatus 100 receives updated data D1 corresponding to LBA L01 from the host 110 to replace the data D1 corresponding to the same LBA L01 stored in block A. However, the data D1 originally stored in PBA A01 in block A can not be overwritten or directly erased, therefore it has to be labeled as “pseudo-erased” and would be actually erased at the proper time. Further, the 120 establishes another new block B in the flash chip 104 for the updated data D1 to be written in (for example, written in PBA B01), and alters the correspondence between the LBA and PBA of the translation table.
The complete updating process further comprises merging the un-updated data D0, D2˜D4 in block A with the updated data D1 in block B (to be discussed later), and “real-erasing” block A to free up space in the flash chip 104. However, at the time of real-erasing, the flash memory apparatus 100 can not be written to or read from so that the performance thereof is influenced. Therefore, it may be desirable in some applications to provide a data managing method for improving the updating performance.